1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the fabrication of highly sophisticated field effect transistors, such as MOS transistors, requiring highly doped shallow junctions formed on the basis of resist masks to provide transistors with different threshold voltages in a semiconductor device.
2. Description of the Related Art
The manufacturing process for integrated circuits continues to improve in several ways, driven by the ongoing efforts to scale down the feature sizes of the individual circuit elements. A key issue in developing integrated circuits of increased packing density and enhanced performance is the scaling of transistor elements, such as MOS transistor elements, to provide the great number of transistor elements that may be necessary for producing modern logic and memory devices. One important aspect in manufacturing field effect transistors having reduced dimensions is the reduction of the length of the gate electrode that controls the formation of a conductive channel separating the source and drain regions of the transistor element. The source and drain regions of the transistor element are conductive semiconductor regions including dopants of an inverse conductivity type compared to the dopants in the surrounding crystalline active region, e.g., a substrate or a well region.
Although the reduction of the gate length is beneficial for obtaining smaller and faster transistor elements, it turns out, however, that a plurality of issues are additionally involved to maintain proper transistor performance for a reduced gate length. One challenging task in this respect is the provision of shallow junction regions, i.e., source and drain regions, which nevertheless exhibit a high conductivity so as to minimize the resistivity in conducting charge carriers from the channel to a respective contact area of the drain and source regions. The requirement for shallow junctions having a high conductivity is commonly met by performing an ion implantation sequence so as to obtain a high dopant concentration having a profile that varies laterally and in depth.
Generally, the ion implantation process is a viable technique for introducing certain dopant species, such as P-type dopants, N-type dopants and the like, into specified device areas, which are usually defined by appropriate implantation masks, such as resist masks and the like. During the definition of active transistor regions, such as P-wells and N-wells, and during the formation of the actual drain and source dopant profiles, respective resist masks are typically provided to selectively expose and cover the device areas so as to introduce the required type of dopant species. That is, the respective implant species is introduced into non-covered device portions while the resist material blocks the dopant species and prevents dopant penetration into covered device portions, wherein the average penetration depth is determined by the implantation energy for a given implant species and a given material composition of the device area, while the dopant concentration is determined by the implantation dose and the implantation duration. Thereafter, the resist mask is removed and a further implantation process may be performed according to device requirements, e.g., for transistors with different threshold voltages on the basis of a newly formed resist mask. Hence, a plurality of implantation processes are to be performed during the formation of transistor elements, thereby also requiring a plurality of resist removal processes. Due to the demand for extremely shallow junctions, i.e., source and drain dopant profiles, in particular in portions located in the vicinity of the channel region, which are also referred to as source and drain extensions, moderately low implantation energies at high doses are to be used, thereby resulting in specific difficulties during the resist removal process, in particular in devices comprising transistors with different threshold voltages as the high-dose implantation and the removal process has to be performed repeatedly, as will be described with reference to FIGS. 1a-1e in more detail.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in a manufacturing stage in which gate electrode structures 110, 120, 130, 140 may be provided with lateral dimensions of, for instance, 50 nm and less. In this manufacturing stage the device 100 typically comprises a substrate 101 in combination with a semiconductor layer 102, such as a silicon layer, in which a plurality of active regions 112, 122, 132, 142 are provided. Generally, an active region is to be understood as a semiconductor region of the layer 102 in and above which one or more transistors have to be formed. In FIG. 1a, the active regions 122, 142 represent the active regions of P-channel transistors, and the active regions 112, 132 represent the active regions of N-channel transistors. The active regions 112, 122, 132, 142 are laterally delineated by an appropriately dimensioned and shaped isolation structure 103, for instance provided in the form of a shallow trench isolation. The gate electrode structures 120, 140 may represent gate electrode structures of the P-channel transistors to be formed in and above the active regions 122, 142 while the gate electrode structures 110, 130 represent gate electrode structures of the N-channel transistors to be formed in and above the active regions 112, 132. In the manufacturing stage shown, the gate electrode structures 110, 120, 130, 140 comprise a gate dielectric material 113, 123, 133, 143, respectively, which may have incorporated therein a gate dielectric material comprising silicon oxide, silicon oxynitride and/or high-k dielectric materials, such as hafnium oxide, hafnium silicate, zirconium oxide and the like. The high-k dielectric materials may be implemented so as to provide a total dielectric constant that is 10.0 and higher. Furthermore, a metal-containing electrode material (not shown), such as titanium nitride and the like, is typically provided in combination with the high-k dielectric material in order to obtain the required threshold voltage characteristics and the like. It should be noted, however, that the materials in the gate electrode structures 110, 130 on the one hand, and in the gate electrode structures 120, 140 on the other hand, may differ in their material composition, for instance with respect to a work function metal species, since typically different work functions are required for the gate electrode structures of transistors of different conductivity type. Furthermore, a silicon-based electrode material 111, 121, 131, 141 is provided in combination with a dielectric cap layer (not shown) or cap layer system, for instance comprising silicon nitride, silicon dioxide and the like. Furthermore, a spacer structure 114, 124, 134, 144, for instance comprised of one or more silicon nitride layers and the like, are formed on sidewalls of the electrode materials 111, 121, 131, 141 and the sensitive materials 113, 123, 133 143 in the gate electrode structures 110, 120, 130, 140. Additionally, a resist mask 104 is formed above the active regions 112, 122, 142.
The device 100 as shown in FIG. 1a may be formed on the basis of the following process strategy. The isolation structure 103 is formed by applying sophisticated lithography, etch, deposition, anneal and planarization techniques in order to form trenches and fill the trenches with an appropriate dielectric material, thereby also defining the lateral size and shape of the active regions 112, 122, 132, 142. After incorporating any dopant species in accordance with the overall device requirements, the gate electrode structures 110, 120, 130, 140 are formed, which may require complex deposition and patterning processes in order to provide the gate materials for the various transistor types. That is, since typically different work function metal species have to be provided for transistors of different conductivity type, a corresponding deposition, masking and patterning regime is applied in this manufacturing stage. Subsequently the gate layer stack is patterned by using sophisticated lithography and etch strategies, thereby finally obtaining the gate electrode structures 110, 120, 130, 140 with the desired critical dimensions, i.e., with a gate length of 50 nm and significantly less in sophisticated applications. Next, a spacer layer is deposited followed by the etching of the spacer layer in order to obtain the spacer elements 114, 124, 134, 144 of the gate electrode structures 110, 120, 130, 140. It should be appreciated that the spacer structures may be used for confining sensitive gate materials in particular when high-k materials are used and may also act as offset spacer elements for appropriately defining the lateral and vertical dopant profiles in the active region 132 and in further advanced manufacturing stages in the active regions 112, 122, 142.
At the manufacturing stage depicted in FIG. 1a, the active regions 112, 122, 142 representing transistors with different threshold voltages are covered by a resist mask 104 and a high-dose implantation sequence 105 is performed that may comprise a pre-amorphization, a source and drain extension implantation, extra diffusion engineering implantations and halo implantations to define source and drain extension regions 125 and halo regions 127 in the active region 132. The halo regions 127 may be provided with a dopant profile appropriate for adjusting the desired threshold voltage of the transistor to be formed in and above the active region 132. During the high-dose implantation steps of the implantation sequence 105, an implant region 139 exhibiting a high concentration of the implanted species is formed in an upper region of the resist mask 104, in particular due to the low-energy of the source and drain extension implantation process.
FIG. 1b schematically illustrates the device 100 in a further advanced process stage in which the resist mask 104 (FIG. 1a) is removed from the active regions 112, 122 and 142. A resist strip process is performed in order to remove the resist mask 104, wherein the removal process may be configured as a plasma process based on, e.g., oxygen, and a further reactive component, such as fluorine in the form of carbon hexafluoride, in order to etch through the implant region 139 of the resist mask 104. During the removal process, exposed surface portions within the active region 132 may be damaged by the reactive components contained in the ambient of the removal process, thereby resulting in a significant material removal as indicated by the dashed line 128. For instance, carbon fluoride is well known to remove silicon, silicon dioxide and the like during a corresponding plasma-based process, which may thus result in a significant amount of material loss in respective exposed device areas, which may impose significant issues during further manufacturing stages with respect to appropriately adjusting the overall transistor characteristics, in particular when highly scaled devices are considered. For example, a material loss of up to a thickness of approximately 2 nm may occur during the removal process and subsequent chemical cleaning processes for removing any residuals 129 of the resist mask 104. An according material loss is in general not acceptable for devices of technologies of 45 nm and beyond. In particular, the significant material loss of exposed device areas may not only result in corresponding thickness fluctuations, depending on the specific process conditions in various device regions, but may also result in a significant loss of dopants, thereby directly influencing the transistor performance. Thus, the resist strip process is typically adjusted with regard to the amount of material removed in the active regions by reducing the duration of plasma and chemical cleaning processes to achieve only a moderate material loss which is acceptable with regard to device performance and production yield.
As a consequence, due to the reduced duration of the plasma and chemical cleaning processes, the number of residuals 129 remaining on the substrate surface may increase so that subsequent process steps, such as, e.g., further implantation steps, may be adversely affected. Thus, the resist removal process is optimized to obtain a moderate material loss and a low count of resist residuals resulting in an acceptable device performance and production yield.
FIG. 1c schematically illustrates the device 100 in a further advanced manufacturing stage wherein a further implantation sequence 165 is performed to provide an appropriate dopant profile in the active region 112, representing a transistor of the same conductivity type (N-type) as the active region 132 but with a different threshold voltage. A resist mask 164 covering the active regions 122, 132, 142 and exposing the active region 112 is formed. The implantation sequence 165 that may again comprise a pre-amorphization, a source and drain extension implantation, extra diffusion engineering implantations and one ore more halo implantation steps to define source and drain extension regions 125 and halo regions 127 in the active region 112 is performed. The halo regions 127 may be provided with a dopant profile appropriate for adjusting the desired different threshold voltage of the transistor to be formed in and above the active region 112. During the implantation sequence 165, the resist residuals 129 may negatively influence, e.g., the obtained dopant profile so that an implant modification 138 may occur. During the further high-dose implantation steps of the implantation sequence 165, a corresponding implant region 139 is also formed in the upper portion of resist mask 164. Consequently, removal of the resist mask 164 is also impeded as described with reference to resist mask 104 of FIG. 1a. Thus, due to the additional high-dose implantation sequence 165 and the additional impeded resist removal step performed to provide transistors with a different threshold voltage, the performance of the resulting device 100 and the achieved production yield may be further deteriorated.
FIG. 1d schematically illustrates the device 100 after removal of the resist mask 164 (FIG. 1c). A further resist mask 174 is formed covering the active regions 112, 132, 142 and exposing the active region 122 during a further high-dose implantation sequence 175 performed to provide an appropriate dopant profile in the active region 122, representing a transistor of a different conductivity type, such as a P-channel transistor. Due to the additional high-dose implantation sequence 175 and the additional resist removal step performed to provide transistors of a different conductivity type, the performance of the resulting device 100 and the achieved production yield may be further deteriorated.
FIG. 1e schematically illustrates the device 100 after removal of the resist mask 174 (FIG. 1d). A further resist mask 184 is formed covering the active regions 112, 122, 132 and exposing the active region 142 during a further high-dose implantation sequence 185 performed to provide an appropriate dopant profile in the active region 142, representing a P-channel transistor with a different threshold voltage. Subsequently, the resist mask 184 may be removed and, as discussed with regard to FIG. 1b, the removal of the resist mask 184 may also be impeded due to the atoms incorporated in the implant region 139 by the performed high-dose implantation processes.
Consequently, each additional high-dose implantation step requiring an additional resist mask increases the amount of residuals which may adversely affect the performance of the finally obtained device. Thus, for example, in CMOS devices comprising three different threshold voltages, such as, e.g., typical low, standard and high threshold voltages, the device performance may be substantially influenced, in particular when devices comprising transistors with a gate length of 50 nm and less are formed.
In view of the above-described situation, a need exists for an enhanced technique for reducing the number of defects caused by residuals of removed resist materials during various manufacturing stages in forming highly scaled semiconductor devices.